SED navigation bar go to NIST home page SED Home Page SED Contacts SED Projects SED Products and Publications Search SED Pages
Invited Session: Statistics at SEMATECH

Invited Session: Statistics at SEMATECH

Organizer: Paul Tobias, SEMATECH
Session Chair: George Milliken, Kansas State Univ.
 

Identifying the Source of Light Point Defects

Jack E. Reece
Statistical Methods Group, SEMATECH

Georgia L. Dempsey
Process Engineering Group, SEMATECH

The Semiconductor Industry faces significant challenges in the manufacture of integrated circuits using steadily shrinking feature sizes. Advanced process development today requires feature sizes nominally 0.35 microns, while the immediate future promises features less than 0.2 microns. A primary concern in these and other processes is contamination in the form of particles or other defects on the wafer surface. In this study, Light Point Defects (LPD's) on the silicon surface provided a measure of surface defects.

The processing of silicon wafers for a specific customer was producing an unacceptably large number of LPD's. Some evidence suggested that the crystal structure of the wafers was responsible; but the possibility existed that the cleaning processes used at SEMATECH were responsible. Comparing the behavior of several wafer types in the "route" used to clean wafers at SEMATECH was somewhat easier than exploring the cleaning process itself.

Therefore, this paper describes the experiment used to separate contributions of the cleaning process from contributions due to wafer crystal structure. A key element was providing the proper sources of replication to allow estimates of statistical significance in the presences of extremely limited wafer resources.

[Jack E. Reece, Statistical Methods Group, SEMATECH, 2706 Montopolis Drive, Austin, TX 78741-6499 USA; jack.reece@sematech.org ]

 

Deciding Among Competing Process Flows

Georgia L. Dempsey
Process Engineering Group, SEMATECH

Jack E. Reece
Statistical Methods Group, SEMATECH

A common challenge in semiconductor manufacturing is choosing the best sequence of process steps among several alternatives to assure that an integrated process flow produces optimum results. Quite often the choice made for one process step can affect the choice best suited for a subsequent process step -- that is, factors can interact across separate process steps. In this example, alternative process existed for each of three sequential steps in a particular flow. Preliminary evidence suggested that alternative processes in each of the three steps considered could reduce defectivity (defects/cm**2 on the wafer surface). However, committing the process line to the alternative techniques required confirmation that the alternative processes when integrated were truly superior to the existing processes.

This paper describes the alternative experimental plans considered for this study and the results found that led to the implementation of the appropriate integrated flow process. The key to this experiment was recognition of its strip plot structure. The design chosen allowed proper replication for estimation of the correct experimental errors to allow proper estimates of significance, while making best use of wafer resources.

[Georgia L. Dempsey, Process Engineering Group, SEMATECH, 2706 Montopolis Drive, Austin, TX 78741-6499 USA; georgia.dempsey@sematech.org ]

Date created: 6/5/2001
Last updated: 6/21/2001
Please email comments on this WWW page to sedwww@cam.nist.gov.