Invited Session: Response Surface Modeling

Organizer: Jayant Kalagnanam, Carnegie Mellon Univ.

Session Chair: Jerry Sacks, National Institute of Statistical Sciences

IC Quality as a High-Dimensional Response Surface

Andrzej J. Strojwas
Dept. of Electrical & Computer Engineering, Carnegie Mellon Univ.

ICs are typically fabricated on single crystal silicon wafers. The fabrication process itself consists of a well defined sequence of 150 to 300 process steps. The steps are designed to introduce and redistribute impurities in the wafer or alter the topography of the wafer. Most of these process steps are performed on batches of 25 to 50 wafers. The correctness of an individual process step is assessed by taking in-line measurements after that step. Typically, these in-lines are electrical and physical measurements characterizing the quality of the ICs on the wafer. The cycle time for producing a single batch of wafers may be as high as 6 to 8 weeks.

From a quality standpoint, the problem is to determine the very best levels of each of the possible control variables, in order to ensure the highest yields and most competitive product. This is intrinsically difficult, since the optimal setpoints must be determined from sparse experimental data and computer simulations of the process. Is is also crucial to monitor the IC fabrication process to detect and diagnose the most likely reasons for the decrease in yield. Both problems can be cast as an application of high-dimensional response surface analysis, which enables practitioners to use strategies and tools that are currently active research areas in modern statistical theory.

[Andrzej J. Strojwas, Dept. of Electrical & Computer Engineering, Carnegie Mellon Univ., Pittsburgh, PA 15213 USA; ajs@gauss.ece.cmu.edu ]

The Comparative Performances of New Wave Response Surface Analyses: An IC Example

David Banks
Dept. of Statistics, Carnegie Mellon Univ.

The last decade has seen an explosion of new statistical procedures for nonparametric response surface analysis. Currently, our inventiveness has outrun our comparativeness, and no one yet has a clear understanding of exactly when some procedures work better than others. This talk repairs that deficiency by presenting research that enables comparative evaluation of MARS, CART, ACE, AVAS, PPR, GAM, Loess, and neural nets across a body of standard problems. It establishes guidelines for when particular methods outperform others, and indicates the degree to which users can rely upon the results of these experimental methods.

To illustrate the results, all eight of the methods under evaluation are applied to data generated from PDFAB, a statistical process simulator from PDF Solutions Inc., employed here to emulate a 0.8 micron CMOS process. I_d current in the NMOS device is the quality variable of interest. There are 22 explanatory variables, of which ten are thought to have a strong functional relationship to the response over the operating region. The results from each procedure are assessed against each other and against expert knowledge, leading to a better understanding of which methods perform well in this problem domain.