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Invited Session: Integrated Circuit Burn-in Issues

Invited Session: Integrated Circuit Burn-in Issues

Organizer/Session Chair: Way Kuo, Texas A & M Univ.

Problems Associated with Burn-in Tests

Dave Grosch, Jon Butkus
Microelectroincs Div., IBM Corporation

Problems that will be discussed include thermal runaway; Power consumption per device under test; switching noise; circuit function at stress conditions; cost; and many others that are pertinent to stress test and burn-in of microelectronics products.

[Dave Grosch, IBM Corporation, Dept. G62, 1000 River Rd., Essex Jct. Vermont 05452 USA; ]


Some Models in Burn-in

Jie Mi
Dept. of Statistics, Flordia International Univ.

In order to reduce early failure of products, burn-in procedure has been used in industry. Burn-in can eliminate defect products and consequently improve the outgoing quality of products. Burn-in is appropriate when product has a decreasing failure rate. More general, burn-in can also be applied fruitfully when the failure rate of product exhibits a bathtub shape. Without consideration of cost, burn-in can be used to maximize certain reliability characteristics. With consideration of cost, it is needed to balance the cost of burn-in, the cost and gain from field operation. Various cost models are set up. It is the concern of this talk to determine for how long products should undergo burn-in in order to optimize a particular reliability characteristic or the average cost.

[Jie Mi, Dept. of Statistics, Florida International Univ., Miami, FL 33199 USA;

Date created: 6/5/2001
Last updated: 6/21/2001
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